Symbolic Veriication with Gap-order Constraints

Speciication and Veriication of Temporal Information Using Presburger Formulas

We present a novel set of tools for performing symbolic timing veriication of timing diagrams. The tools are multipurpose with uses in veriication, derivation of synthesis constraints, and design evaluation. Our methodology is based on techniques for manipulating Presburger formulas. We demonstrate via examples that Presburger formulas are very expressive and our veriication results argue that ...

Symbolic Verification with Gap-Order Constraints

Automated Verification of Concurrent Linked Lists with Counters

We present an automated veriication technique for veriica-tion of concurrent linked lists with integer variables. We show that using our technique one can automatically verify invariants that relate (unbounded) integer variables and heap variables such as head 6 = null ! numItems > 0. The presented technique extends our previous work on composite symbolic representations with shape analysis. Th...

Automatic Symbolic Verification of Embedded Systems

We present a model-checking procedure and its implementation for the automatic veriication of embedded systems. The system components are described as Hybrid Automata|communicating machines with nite control and real-valued variables that represent continuous environment parameters such as time, pressure, and temperature. The system requirements are speciied in a temporal logic with stop watche...

A simple theorem prover based on symbolic trajectory evaluation and BDD's

Formalhardware veriication based on symbolic trajectory evaluation shows considerable promise in verifying medium to large scale VLSI designs with a high degree of automation. However, in order to verify today's designs, a method for composing partial veriication results is needed. One way of accomplishing this is to use a general purpose theorem prover to combine the veri-cation results obtain...